This application claims priority from Korean Priority Document No. 1999-51338, filed on Nov. 18, 1999 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to an operation mode circuit of a semiconductor memory device, and a method for setting thereof. More particularly, the invention relates to an operation mode setting circuit which can prevent a malfunction in a user mode of a mode register set circuit of a semiconductor memory device, which can previously program an operation of a Synchronous DRAM such as SDRAM.
2. Description of the Related Arts
Generally, a Sync DRAM or Rambus DRAM can set row access time, column access time or burst length as positive number times, have a register determine a bandwidth, and test an operation mode of a circuit according to programs of the register. The register is referred to as a mode register, and the circuit is referred to as a mode register set (MRS) circuit.
FIG. 1 is a block diagram showing an operation mode setting circuit of a conventional semiconductor memory device. FIG. 2 is a circuit diagram showing a mode control signal generator. And FIG. 3 is a timing diagram for explaining the operation of the circuit of FIG. 1.
Conventionally, external address signals A0xcx9cA11 are latched to a mode register 10. The latched internal address signals IA0xcx9cIA11 are provided to a mode control signal generator 12 and an output unit 14. As shown in FIG. 2, the mode control signal generator 12 makes a combination of address signals IAl and IAm associated with a test mode, and address signals IAixcx9cIAk associated with a MRS among the inputted internal address signals. The mode control signal generator 12 then judges a present operation mode to be either a test mode or user mode, and then outputs a corresponding mode control signal MRSET or TMSET. In this case, these mode control signals are enabled in response to a Pulsed Write Command signal PWCBR of the MRS.
The output unit 14 selectively outputs address signals associated with each mode in response to the mode control signal (MRSET or TMSET), and provides to a first decoder 16 or a second decoder 18, depending on whether the mode is regular or test. The first or second decoder 16 or 18 decodes the provided address signals, and then outputs programmed operation mode signals MRSi and TESi, to set an operation mode of a chip.
The test mode is a mode used by the semiconductor chip manufacturer during manufacturing, to test whether the chip is defective. The test mode, however, is meaningless to the eventual customer, who is also considered to be a general user.
A problem arises since general users often program MRS values in a user mode. When they make a mistake, an invalid MRS value or test mode value is often programmed.
Accordingly, as disclosed in the Korean Patent Publication No. 1999-3104, if an invalid MRS is set in a user mode, the invalid MRS is changed to a valid MRS thereafter, and then the valid MRS is reset in a user mode. In other words, in case a test mode is set in a user mode by mistake, if a user mode is reset, a test mode and a user mode are set in the same time. As a result, the chip makes an error, since the chip recognizes that a user mode is not set. Therefore, the publication discloses technology for resetting a test mode, in case of resetting a user mode after a test mode is set.
However, strictly speaking, the above mentioned publication is not to reset a test operation in the state that a chip is operating in a test mode, but to reset a test mode setting signal. Therefore, it requires much time, from after the test mode setting signal is reset until a test operation is completely reset in response to the reset operation.
That is, it is inconvenient to reset a normal operation after waiting until an entering operation is completely reset, and then repaired to a normal status.
To solve the problem of the prior art described above, an object of the present invention is to provide an operation mode setting circuit of a semiconductor memory device and a method for setting thereof, which can prevent a test mode from being set in a user mode. The invention blocks a test mode, even in case a user sets a test mode in a user mode by mistake. This improves the convenience of users.
The invention blocks the test mode by assuring that the test mode control signal is controlled also by an additional external signal. Preferably, the external control signal is a clock enable signal or data input/output control signal. The test mode is blocked in an active area of the clock enable signal. In the preferred embodiment only, an internal control signal is generated from the external control signal.
A circuit of the present invention includes a mode register, an internal control signal generator to generate the internal control signal, a mode control signal generator, an output unit, a first decoder and a second decoder.
A method according to the present invention includes generating internal address signals by inputting external address signals into a mode register. The method also includes generating a test mode control signal or mode register set control signal by combining the internal address signals in response to a mode register set write signal and also to an external control signal. The method additionally includes outputting a corresponding address signal among the internal address signals as a first internal address signal in response to the mode register set control signal, or outputting a corresponding address signal among the internal address signals as a second internal address signal in response to the test mode control signal.